Selection schemes for clock signals exist in a wide variety of forms. A general problem in selection schemes of this nature is the achievement of switching from one clock source to another `on the fly`, that is to say asynchronously relative to any of the clocks without producing any `glitches`, that is to say undesirable transients such as spike pulses in the selected output clock signal. Various solutions to this general problem have been proposed. They generally involve negative edge clocking, asynchronous latches, asynchronously set and cleared flip-flops or gated clocks. Many designs employ some form of feedback path, for example a coupling from the output of a flip-flop to an input thereof. Although such feedback paths, exemplified by U.S. Pat. No. 4,853,653 to Maher may facilitate design from the point of view of minimising the number of gates, in general the existence of feedback paths make a design more difficult to simulate exhaustively and to analyse for edge conditions or lock-up states.